Conventionally, a latch hysteresis receiver circuit is typically used for receiving signals from an external source outside of a die, onto the die, and then translating the signal from an external power supply to an internal power supply. A receiver circuit with hysteresis has different switch point voltages depending on whether the input voltage is going from a logical “0” (low) to a logical “1” (high) or vice versa. The delta (or difference) between the switch point voltages is commonly referred to as hysteresis. It is noted that the low switch point voltage is commonly referred to as the switch point low voltage (VSPL) while the high switch point voltage is commonly referred to as the switch point high voltage (VSPH). Through hysteresis, conventional latch hysteresis receivers are also implemented with noise immunity. In this manner, the latch hysteresis receiver circuit is able to operate properly even when it receives noise as part of an input signal.
It is noted that latch hysteresis receiver circuits may be implemented differently in order to provide particular functions. For example, some latch hysteresis receiver circuits are designed to operate as a low current and low voltage device. For example, a latch hysteresis receiver circuit may operate utilizing battery power where it is desirable to keep power consumption to a minimum in order to extend the life of the battery (or batteries). Additionally, these low power latch hysteresis receiver circuits may be designed to receive a wide range of input voltage signals so that they may be utilized within different circuitry.
FIG. 1 shows a schematic diagram of an example of a conventional latch hysteresis receiver circuit 100 that is designed to receive a wide range of input voltage signals and also operate as a low current and low voltage device. However, there are some disadvantages associated with the conventional latch hysteresis receiver circuit 100. One of the disadvantages is that the latch hysteresis receiver 100 is not able to effectively operate when its switch point low voltage is less than its most positive down level (MPDL) voltage.
One conventional solution is to reduce the current flowing through transistor 114 in order to make it weaker, which can be done by making its length longer decreasing W/L ratio. However, this conventional solution is unable to maintain the switch point low voltage greater than the most positive down level voltage.
Alternatively, another conventional solution is to stack an N-channel MOSFET (metal-oxide semiconductor field-effect transistor) in series with transistor 114 in order to reduce the current flowing through them. However, this conventional solution is also unable to maintain the switch point low voltage above the most positive down level voltage.